1. Technical Field
The present invention relates to a signal output apparatus, a signal detecting apparatus, a test apparatus, an electronic device and a program. More particularly, the present invention relates to a signal output apparatus for outputting a pattern signal, a signal detecting apparatus for detecting a pattern signal input thereto, a test apparatus for testing a device under test, an electronic device and a program.
2. Related Art
A test apparatus for testing a semiconductor device transmits to the semiconductor device a test signal via a transmission path formed by a socket, a cable, a performance board and the like, and receives an output signal output from the semiconductor device via the transmission path as disclosed in, for example, Japanese Patent Application Publication No. 2006-220660.
FIG. 1 illustrates a test signal or output signal which has passed through a transmission path. FIG. 2 illustrates the relation between the phase and the pulse width of the test signal or output signal which has passed through the transmission path.
When the test or output signal has passed through the transmission path, the high frequency components of the signal are cut off. Therefore, the test or output signal has edges with lowered gradients at the receiving end of the transmission path as shown in FIG. 1. When the gradients of the edges are lowered, a pattern with a relatively short pulse width fails to settle. Specifically speaking, in a pattern with a relatively short pulse width, the trailing edge starts before the leading edge reaches a desired level.
Such a pattern in which the trailing edge starts without a settling time may be two-valued by using a predetermined threshold value to generate a logic value signal. In the logic value signal, the phase of the transition timing of the logic value is earlier than in a logic value signal obtained by two-valuing the original pattern. In other words, a pattern with a relatively short pulse width has jitter generated therein as a result of passing through the transmission path, so that the pulse width becomes shorter than the original width. This jitter is referred to as “pattern dependent jitter”. The pattern dependent jitter increases as the pulse width decreases as shown in FIG. 2.
When a test signal suffers from pattern dependent jitter, a test apparatus cannot supply the test signal to a semiconductor device at a designated timing and thus may cause the semiconductor device to perform an operation different from an expected operation. When an output signal suffers from pattern dependent jitter, the test apparatus cannot detect the output signal at a desired timing and thus may wrongly judge that the semiconductor device is defective even though the semiconductor device outputs an expected output signal.